IIgs Bus Timing

The IIgs has two memory clocks: the processor (65816) bus, which connects to the Fast RAM, and the Mega II (Apple II-compatible) bus, which connects to the Slow RAM and peripherals.

The 816 bus clock is identified by the symbol Φ2 and the M2 bus clock is identified by Φ0. The complement of the M2 clock is denoted Φ1. Both clocks are derived from a 14.31818 MHz master clock, which is known as 14M.

In the following description, phase 1 refers to the period where a bus clock is low, and phase 2 refers to the period where the bus clock is high. A time measurement in cycles refers to the number of cycles of 14M.

Mega II bus clock

Frequency	1.023 MHz
Duty cycle	50% (7:7 cycles)
Period	978 ns (14 cycles)
Phase 1	489 ns (7 cycles)
Phase 2	489 ns (7 cycles)

816 bus clock

The 816 clock is irregular and runs different cycles depending on what memory location is accessed.

The normal cycle is used for accesses to Fast RAM or ROM.

Normal cycle

Frequency	2.864 MHz
Duty cycle	60% (2:3 cycles)
Period	349.2 ns (5 cycles)
Phase 1	139.7 ns (2 cycles)
Phase 2	209.5 ns (3 cycles)

The 1.4 MHz cycle is used for refreshing RAM? XXX Verify this, and determine where the refresh takes place.

1.4 MHz cycle

Frequency	1.432 MHz
Duty cycle	80% (2:8 cycles)
Period	698.4 ns (10 cycles)
Phase 1	139.7 ns (2 cycles)
Phase 2	558.7 ns (8 cycles)

The Mega II synchronization cycle is used when a Slow RAM or shadowed write access is made in order to match the Mega II clock. This cycle consists of a variable-length Φ2 extension period, where the Φ2 clock signal is held high from the 816 cycle's phase 2 until the phase 2 of the next M2 bus cycle. At that point, Φ2 will follow the M2 bus clock for its phase 2.

The IIgs does not use the RDY signal for synchronization.

Mega II sync cycle

Previous cycle Phase 2 extension	Variable-length
Phase 1 M2 only; Φ2 held high	489 ns (7 cycles)
Phase 2	489 ns (7 cycles)